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an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. advance information for pre-production products; subject to change without notice. tmux1574 scds391 ? october 2018 tmux1574 low-capacitance, 2:1 (spdt) 4-channel, powered-off protected switch with 1.8 v logic 1 1 features 1 ? wide supply range: 1.5 v to 5.5 v ? low on-capacitance: 7.5 pf ? low on-resistance: 2 ? high bandwidth: 1.5 ghz ? -40 c to +125 c operating temperature ? 1.8 v logic compatible ? supports input voltage beyond supply ? bidirectional signal path ? fail-safe logic ? powered-off protection up to 3.6 v signals ? pinout compatible to sn74cbtlv3257 2 applications ? servers ? data center switches & routers ? wireless infrastructure ? pc/notebooks ? building automation ? grid infrastructure ? epos ? appliances ? flash memory sharing ? jtag multiplexing ? spi multiplexing 3 description the tmux1574 is a complementary metal-oxide semiconductor (cmos) switch. the tmux1574 offers 2:1 spdt switch configuration with 4-channels. wide operating supply of 1.5 v to 5.5 v allows for use in a wide array of applications from servers and communication equipment to industrial applications. the device supports bidirectional analog and digital signals on the source (sxa, sxb) and drain (dx) pins and can pass signals above supply up to v dd x 2, with a maximum of 5.5 v. powered-off protection up to 3.6 v on the signal path of the tmux1574 provides isolation when the supply voltage is removed (v dd = 0 v). without this protection feature, switches can back-power the supply rail through an internal esd diode and cause potential damage to the system. fail-safe logic circuitry allows voltages on the logic control pins to be applied before the supply pin, protecting the device from potential damage. all control inputs have 1.8 v logic compatible thresholds, ensuring both ttl and cmos logic compatibility when operating in the valid supply voltage range. device information (1) part number package body size (nom) tmux1574 tssop (16) 5.00 mm 4.40 mm uqfn (16) 2.60 mm x 1.80 mm (1) for all available packages, see the package option addendum at the end of the data sheet. spacer spacer application example simplified schematic processor gnd v dd v dd v i/o 1.8v logic i/o sel gnd jtag debug, spi, gpio d1 d2 d3 d4 ram cpu peripherals 0.1f en s1b s2b s3b s4b spi / jtag / uart device #2 miso / tdi / gpio mosi / tdo / gpio sclk / tck / gpio ss / tms / gpio s1a s2a s3a s4a spi / jtag / uart device #1 miso / tdi / gpio mosi / tdo / gpio sclk / tck / gpio ss / tms / gpio tmux1574 sel s1a d1 s1b s2a s2b s3as3b s4a s4b en logic control d2 d3 d4 advance information technical documents support &community ordernow productfolder tools & software
2 tmux1574 scds391 ? october 2018 www.ti.com product folder links: tmux1574 submit documentation feedback copyright ? 2018, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 pin configuration and functions ......................... 3 6 specifications ......................................................... 4 6.1 absolute maximum ratings ...................................... 4 6.2 esd ratings .............................................................. 4 6.3 recommended operating conditions ....................... 4 6.4 thermal information .................................................. 4 6.5 electrical characteristics ........................................... 5 6.6 dynamic characteristics ........................................... 6 6.7 timing requirements ................................................ 7 7 parameter measurement information .................. 8 7.1 on-resistance .......................................................... 8 7.2 off-leakage current ................................................. 8 7.3 on-leakage current ................................................. 9 7.4 transition time ......................................................... 9 7.5 t on (en) and t off (en) time .................................... 10 7.6 t on (vdd) and t off (vdd) time ................................ 10 7.7 charge injection ...................................................... 11 7.8 capacitance ............................................................ 11 7.9 off isolation ............................................................. 12 7.10 channel-to-channel crosstalk .............................. 12 7.11 bandwidth ............................................................. 13 8 detailed description ............................................ 14 8.1 overview ................................................................. 14 8.2 functional block diagram ....................................... 14 8.3 feature description ................................................. 14 8.4 device functional modes ........................................ 15 8.5 truth tables ............................................................ 15 9 application and implementation ........................ 16 9.1 application information ............................................ 16 9.2 typical application ................................................. 16 10 power supply recommendations ..................... 17 11 layout ................................................................... 18 11.1 layout guidelines ................................................. 18 11.2 layout example .................................................... 19 12 device and documentation support ................. 20 12.1 documentation support ........................................ 20 12.2 receiving notification of documentation updates 20 12.3 community resources .......................................... 20 12.4 trademarks ........................................................... 20 12.5 electrostatic discharge caution ............................ 20 12.6 glossary ................................................................ 20 13 mechanical, packaging, and orderable information ........................................................... 21 4 revision history note: page numbers for previous revisions may differ from page numbers in the current version. date revision notes october 2018 * preliminary draft. advance information
3 tmux1574 www.ti.com scds391 ? october 2018 product folder links: tmux1574 submit documentation feedback copyright ? 2018, texas instruments incorporated 5 pin configuration and functions pw package 16-pin tssop top view rsv package 16-pin uqfn top view (1) i = input, o = output, i/o = input and output, p = power pin functions pin type (1) description name tssop uqfn sel 1 15 i select pin: controls state of switches (logic low = sxa to dx, logic high = sxb to dx) s1a 2 16 i/o source pin 1a. can be an input or output. s1b 3 1 i/o source pin 1b. can be an input or output. d1 4 2 i/o drain pin 1. can be an input or output. s2a 5 3 i/o source pin 2a. can be an input or output. s2b 6 4 i/o source pin 2b. can be an input or output. d2 7 5 i/o drain pin 2. can be an input or output. gnd 8 6 p ground (0 v) reference d3 9 7 i/o drain pin 3. can be an input or output. s3b 10 8 i/o source pin 3b. can be an input or output. s3a 11 9 i/o source pin 3a. can be an input or output. d4 12 10 i/o drain pin 4. can be an input or output. s4b 13 11 i/o source pin 4b. can be an input or output. s4a 14 12 i/o source pin 4a. can be an input or output. en 15 13 i active low enable: when this pin is high, all switches are turned off. when this pin is low, sel pin controls the signal path selection. vdd 16 14 p positive power supply. this pin is the most positive power-supply potential. for reliable operation, connect a decoupling capacitor ranging from 0.1 f to 10 f between v dd and gnd. 1 sel 16 vdd 2 s1a 15 en 3 s1b 14 s4a 4 d1 13 s4b 5 s2a 12 d4 6 s2b 11 s3a 7 d2 10 s3b 8 gnd 9 d3 not to scale advance information 1 s1b 2 d1 3 s2a 4 s2b 5 d2 6 gnd 7 d3 8 s3b 9 s3a 10 d4 11 s4b 12 s4a 13 en 14 vdd 15 sel 16 s1a not to scale
4 tmux1574 scds391 ? october 2018 www.ti.com product folder links: tmux1574 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions . exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) the algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum. 6 specifications 6.1 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) (2) min max unit v dd supply voltage ? 0.5 6 v v sel or v en logic control input pin voltage (sel or en) ? 0.5 6 v i sel or i en logic control input pin current (sel or en) ? 30 30 ma v s or v d source or drain pin voltage ? 0.5 6 v i s or i d (cont) source and drain pin continuous current: (sxa, sxb, dx) ? 25 25 ma t stg storage temperature ? 65 150 c t j junction temperature 150 c (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 6.2 esd ratings value unit v (esd) electrostatic discharge human body model (hbm), per ansi/esda/jedec js-001 (1) 2000 v charged-device model (cdm), per jedec specification jesd22-c101 (2) 750 (1) v s_off and v d_off refers to the voltage at the source or drain pins when supply is less than 1.5 v 6.3 recommended operating conditions min max unit v dd supply voltage 1.5 5.5 v v s or v d signal path input/output voltage (source or drain pin), v dd 1.5 v 0 5.5 v v s_off or v d_off signal path input/output voltage (source or drain pin), v dd < 1.5 v (1) 0 3.6 v v sel or v en logic control input voltage ( en, sel) 0 5.5 v t a ambient temperature ? 40 125 o c (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report. 6.4 thermal information thermal metric (1) device device unit pw (tssop) rsv (uqfn) 16 pins 16 pins r ja junction-to-ambient thermal resistance 117.4 tbd c/w r jc(top) junction-to-case (top) thermal resistance 47.9 tbd c/w r jb junction-to-board thermal resistance 63.7 tbd c/w jt junction-to-top characterization parameter 6.9 tbd c/w y jb junction-to-board characterization parameter 63.1 tbd c/w r jc(bot) junction-to-case (bottom) thermal resistance n/a tbd c/w advance information
5 tmux1574 www.ti.com scds391 ? october 2018 product folder links: tmux1574 submit documentation feedback copyright ? 2018, texas instruments incorporated 6.5 electrical characteristics v dd = 1.5 v to 5.5 v, gnd = 0v, t a = ? 40 c to +125 c typical values are at v dd = 3.3 v, t a = 25 c, (unless otherwise noted) parameter test conditions min typ max unit supply v dd power supply voltage 1.5 5.5 v i dd active supply current v in = 0 v, 1.4v or v dd v s = 0 v to 5.5 v 40 68 a i dd_stan dby supply current when disabled v en = 1.4v or v dd v s = 0 v to 5.5 v 7.5 15 a dc characteristics r on on-state resistance v s = 0 v to v dd i sd = 8 ma refer to on-state resistance figure 2 4.5 ? r on on-state resistance v s = v dd *2 v s(max) = 5.5 v i sd = 8 ma refer to on-state resistance figure 2 4.5 ? r on on-state resistance match between channels v s = v dd i sd = 8 ma refer to on-state resistance figure 0.07 ? r on (flat) on-state resistance flatness v s = 0 v to v dd i sd = 8 ma refer to on-state resistance figure 1 1.8 ? i poff power-off i/o pin leakage current v dd = 0 v v s = 0 v to 3.6 v v d = 0 v refer to ipoff leakage figure ? 2 0.01 2 a i s(off) i d(off) off leakage current switch off v d = 0.8*v dd / 0.2*v dd v s = 0.2*v dd / 0.8*v dd refer to off leakage figure ? 100 1 100 na i d(on) i s(on) on leakage current switch on v d = 0.8*v dd / 0.2*v dd , s pins floating or v s = 0.8*v dd / 0.2*v dd , d pins floating refer to on leakage figure ? 50 1 50 na logic inputs v ih input logic high 1.2 5.5 v v il input logic low 0 0.45 v i ih input high leakage current v sel = 1.8 v, v dd 1 2 a i il input low leakage current v sel = 0 v ? 2 ? 0.2 a r pd internal pull-down resistor on logic pins 6 m c i logic input capacitance v sel = 0 v, 1.8 v or v dd f = 1 mhz 3.5 pf advance information
6 tmux1574 scds391 ? october 2018 www.ti.com product folder links: tmux1574 submit documentation feedback copyright ? 2018, texas instruments incorporated 6.6 dynamic characteristics v dd = 1.5 v to 5.5 v, gnd = 0v, t a = ? 40 c to +125 c typical values are at v dd = 3.3 v, t a = 25 c, (unless otherwise noted) parameter test conditions min typ max unit c off source and drain off capacitance v s = 2.5 v v sel = 0 v f = 1 mhz refer to capacitance figure switch off 3.5 pf c on source and drain on capacitance v s = 2.5 v v sel = 0 v f = 1 mhz refer to capacitance figure switch on 7.5 pf q c charge injection v s = v dd /2 r s = 0 , c l =1 nf refer to charge injection figure switch on 10 pc o iso off isolation r l = 50 f = 100 khz refer to off isolation figure switch off ? 90 db r l = 50 f = 1 mhz refer to off isolation figure switch off ? 60 db x talk channel to channel crosstalk r l = 50 f = 100 khz refer to crosstalk figure switch on ? 90 db bw bandwidth r l = 50 refer to bandwidth figure switch on 1.5 ghz i loss insertion loss r l = 50 f = 1 mhz refer to insertion loss figure switch on ? 0.5 db advance information
7 tmux1574 www.ti.com scds391 ? october 2018 product folder links: tmux1574 submit documentation feedback copyright ? 2018, texas instruments incorporated 6.7 timing requirements v dd = 1.5 v to 5.5 v, gnd = 0v, t a = ? 40 c to +125 c typical values are at v dd = 3.3 v, t a = 25 c, (unless otherwise noted) parameter test conditions min nom max unit t tran transition time from control input v dd = 2.3 v to 5.5 v v s = v dd r l = 200 , c l = 15pf refer to transition timing figure 160 350 ns t tran transition time from control input v dd < 2.3 v v s = v dd r l = 200 , c l = 15pf refer to transition timing figure 180 580 ns t on(en) device turn on time from enable pin v s = v dd r l = 200 , c l = 15pf refer to ton-en & toff-en figure 12 35 s t off(en) device turn off time from enable pin v s = v dd r l = 200 , c l = 15pf refer to ton-en & toff-en figure 50 95 ns t on(vdd) device turn on time (v dd to output) v s = 3.6 v v dd rise time = 1us r l = 200 , c l = 15pf refer to ton-vdd & toff-vdd figure 20 60 s t off(vdd) device turn off time (v dd to output) v s = 3.6 v v dd fall time = 1us r l = 200 , c l = 15pf refer to ton-vdd & toff-vdd figure 1.2 2.7 s t open (bbm) break before make time v s = 1 v r l = 200 , c l = 15pf 0.5 ns t sk(p) inter - channel skew 9 ps t pd propagation delay 130 ps advance information
8 tmux1574 scds391 ? october 2018 www.ti.com product folder links: tmux1574 submit documentation feedback copyright ? 2018, texas instruments incorporated 7 parameter measurement information 7.1 on-resistance the on-resistance of a device is the ohmic resistance between the source (sx) and drain (dx) pins of the device. the on-resistance varies with input voltage and supply voltage. the symbol r on is used to denote on-resistance. the measurement setup used to measure r on is shown in figure 1 . voltage (v) and current (i sd ) are measured using this setup, and r on is computed as shown below with r on = v / i sd : figure 1. on-resistance measurement setup 7.2 off-leakage current source leakage current is defined as the leakage current flowing into or out of the source pin when the switch is off. this current is denoted by the symbol i s (off) . drain leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is off. this current is denoted by the symbol i d (off) . the setup used to measure both off-leakage currents is shown in figure 2 . figure 2. off-leakage measurement setup v dx v s i sd sx v dd v dd s1a gnd d1 v d i d (off) a v s s1b s4a d4 v d i d (off) a v s s4b v dd v dd s1a gnd d1 v d v s s1b i s (off) a v d s1a d1 v d v s s1b i s (off) a v d advance information
9 tmux1574 www.ti.com scds391 ? october 2018 product folder links: tmux1574 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.3 on-leakage current source on-leakage current is defined as the leakage current flowing into or out of the source pin when the switch is on. this current is denoted by the symbol i s (on) . drain on-leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is on. this current is denoted by the symbol i d (on) . either the source pin or drain pin is left floating during the measurement. figure 3 shows the circuit used for measuring the on-leakage current, denoted by i s(on) or i d(on) . figure 3. on-leakage measurement setup 7.4 transition time transition time is defined as the time taken by the output of the device to rise or fall 10% after the select signal has risen or fallen past the logic threshold. the 10% transition measurement is utilized to provide the timing of the device. the time constant from the load resistance and load capacitance can be added to the transition time to calculate system level timing. figure 4 shows the setup used to measure transition time, denoted by the symbol t transition . figure 4. transition-time measurement setup v dd v dd s1a gnd d1 v d i d (on) a s1b s4a d4 v d i d (on) a s4b n.c. n.c. n.c. n.c. v dd v dd s1a gnd d1 s1b s4a d4 s4b n.c. n.c. n.c. n.c. v s i s (on) a v s i s (on) a v ih v il t transition 10% 90% output 0 v address drive (v sel ) v dd t transition v sel 0 v t r < 5ns t f < 5ns gnd v s output r l c l s1a d1 sel v dd v dd 0.1 f s1b v s output r l c l s4a d4 s4b advance information
10 tmux1574 scds391 ? october 2018 www.ti.com product folder links: tmux1574 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.5 t on (en) and t off (en) time t on (en) time is defined as the time taken by the output of the device to rise to 90% after the enable has fallen past the logic threshold. the 90% measurement is utilized to provide the timing of the device being enabled in the system. figure 5 shows the setup used to measure the enable time, denoted by the symbol t on (en) . t off (en) time is defined as the time taken by the output of the device to fall to 90% after the enable has fallen past the logic threshold. the 90% measurement is utilized to provide the timing of the device being disabled in the system. figure 5 shows the setup used to measure enable time, denoted by the symbol t off (en) . figure 5. turn-on-en and turn-off-en time measurement setup 7.6 t on (vdd) and t off (vdd) time t on (vdd) time is defined as the time taken by the output of the device to rise to 90% after the supply has risen past the supply threshold. the 90% measurement is utilized to provide the timing of the device turning on in the system. figure 6 shows the setup used to measure turn on time, denoted by the symbol t on (vdd) . t off (vdd) time is defined as the time taken by the output of the device to fall to 90% after the supply has fallen past the supply threshold. the 90% measurement is utilized to provide the timing of the device turning off in the system. figure 6 shows the setup used to measure turn off time, denoted by the symbol t off (vdd) . figure 6. turn-on-vdd and turn-off-vdd time measurement setup gnd v dd 0 v supply ramp (v dd ) 1.5 v 1.5 v t on (vdd) t off (vdd) 90% 90% output 0 v v dd v dd 0.1 f v dd v s output r l c l s1a d1 s1b v s output r l c l s4a d4 s4b en advance information gnd v dd 0 v enable drive (v en ) v il v ih t on (en) t off (en) 90% output 0 v t r < 5ns t f < 5ns 90% v dd v dd 0.1 f v s output r l c l s1a d1 s1b v s output r l c l s4a d4 s4b v en en
11 tmux1574 www.ti.com scds391 ? october 2018 product folder links: tmux1574 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.7 charge injection the amount of charge injected into the source or drain of the device during the falling or rising edge of the gate signal is known as charge injection, and is denoted by the symbol q c . figure 7 shows the setup used to measure charge injection from source (sx) to drain (dx). figure 7. charge-injection measurement setup 7.8 capacitance the parasitic capacitance of the device is captured at the source (sx), drain (dx), and select (selx) pins. the capacitance is measured in both the on and off state and is denoted by the symbol c on and c off . figure 8 shows the setup used to measure capacitance. figure 8. capacitance measurement setup advance information v out output v s 0 v v dd q c = c l v out v en gnd output c l d1 v dd v dd 0.1 f v out v en v s s1a s1b output c l d4 v out v s s4a s4b en v dd v dd gnd 1 mhz capacitance meter capacitance is measured at s x , d x , and logic pins during on and off conditions s1a d1 s1b s4a d4 s4b sel logic control en
12 tmux1574 scds391 ? october 2018 www.ti.com product folder links: tmux1574 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.9 off isolation off isolation is defined as the ratio of the signal at the drain pin (dx) of the device when a signal is applied to the source pin (sx) of an off-channel. the characteristic impedance, z 0 , for the measurement is 50 . figure 9 shows the setup used to measure off isolation. use off isolation equation to compute off isolation. figure 9. off isolation measurement setup (1) 7.10 channel-to-channel crosstalk crosstalk is defined as the ratio of the signal at the drain pin (dx) of a different channel, when a signal is applied at the source pin (sx) of an on-channel. the characteristic impedance, z 0 , for the measurement is 50 . figure 10 shows the setup used to measure, and the equation used to compute crosstalk. figure 10. channel-to-channel crosstalk measurement setup (2) gnd network analyzer v out s d 50 ? v sig r l 50 ? v s v dd 0.1f sxa / sxb / dx r l 50 ? network analyzer v dd 0.1f v dd gnd s1a v sig = 200 mvpp v bias = v dd / 2 50 ? v out r l d1 50 ? s4a 50 ? r l d4 v s sxa / sxb / dx 50 ? r l 50 ? r l advance information out s v off isolation 20 log v ? ? ? 1 out s v channel-to-channel crosstalk 20 log v ? ? ? 1
13 tmux1574 www.ti.com scds391 ? october 2018 product folder links: tmux1574 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.11 bandwidth bandwidth is defined as the range of frequencies that are attenuated by less than 3 db when the input is applied to the source pin (sx) of an on-channel, and the output is measured at the drain pin (dx) of the device. the characteristic impedance, z 0 , for the measurement is 50 . figure 11 shows the setup used to measure bandwidth. figure 11. bandwidth measurement setup advance information gnd network analyzer v out s d 50 ? v sig r l 50 ? v s v dd 0.1f v dd sxa / sxb / dx r l 50 ?
14 tmux1574 scds391 ? october 2018 www.ti.com product folder links: tmux1574 submit documentation feedback copyright ? 2018, texas instruments incorporated 8 detailed description 8.1 overview the tmux1574 is a high speed 2:1 (spdt) 4-ch. switch with powered-off protection up to 3.6 v. wide operating supply of 1.5 v to 5.5 v allows for use in a wide array of applications from servers and communication equipment to industrial applications. the device supports bidirectional analog and digital signals on the source (sxa, sxb) and drain (dx) pins. the wide bandwidth of this switch allows little or no attenuation of high-speed signals at the outputs to pass with minimum edge and phase distortion as well as propagation delay. the enable ( en) pin is an active-low logic pin that controls the connection between the source (sxa, sxb) and drain (dx) pins of the device. the select pin (sel) controls the state of all four channels of the tmux1574 and determines which source pin is connected to the drain. fail-safe logic circuitry allows voltages on the logic control pins to be applied before the supply pin, protecting the device from potential damage. all logic control inputs have 1.8v logic compatible thresholds, ensuring both ttl and cmos logic compatibility when operating in the valid supply voltage range. powered-off protection up to 3.6 v on the signal path of the tmux1574 provides isolation when the supply voltage is removed (v dd = 0 v). without this protection feature, the system can back-power the supply rail through an internal esd diode and cause potential damage to the system. 8.2 functional block diagram 8.3 feature description 8.3.1 bidirectional operation the tmux1574 conducts equally well from source (sxa, sxb) to drain (dx) or from drain (dx) to source (sxa, sxb). each channel has very similar characteristics in both directions and supports both analog and digital signals. 8.3.2 beyond supply operation the valid signal path input/output voltage for tmux1574 ranges from gnd to v dd x 2, with a maximum of 5.5 v. 8.3.3 1.8 v logic compatible inputs the tmux1574 has 1.8-v logic compatible control inputs for all switch channels. regardless of the v dd voltage the control input thresholds remained fixed, allowing a 1.8-v processor gpio to control the tmux1574 without the need for an external translator. this saves both space and bom cost. for more information on 1.8 v logic implementations refer to simplifying design with 1.8 v logic muxes and switches tmux1574 sel s1a d1 s1b s2a s2b s3as3b s4a s4b en logic control d2 d3 d4 advance information
15 tmux1574 www.ti.com scds391 ? october 2018 product folder links: tmux1574 submit documentation feedback copyright ? 2018, texas instruments incorporated feature description (continued) 8.3.4 powered-off protection powered-off protection up to 3.6 v on the signal path of the tmux1574 provides isolation when the supply voltage is removed (v dd = 0 v). when the tmux1574 is powered-off the i/os of the device remain in a high-z state. powered-off protection minimizes system complexity by removing the need for power supply sequencing on the signal path. the device performance remains within the leakage performance mentioned in the electrical specifications. for more information on 1.8 v logic implementations refer to eliminate power sequencing with powered-off protection signal switches 8.3.5 fail-safe logic the tmux1574 support fail-safe logic on the control input pins ( en, sel) allowing for operation up to 5.5 v, regardless of the state of the supply pin. this feature allows voltages on the logic control pins to be applied before the supply pin, protecting the device from potential damage. fail-safe logic minimizes system complexity by removing the need for power supply sequencing on the logic control pins. for example, the fail-safe logic feature allows the control pins of the tmux1574 to be ramped to 5.5 v while v dd = 0 v. additionally, the feature enables operation of the tmux1574 with v dd = 1.5 v while allowing the select pins to interface with a logic level of another device up to 5.5 v. 8.4 device functional modes the enable ( en) pin is an active-low logic pin that controls the connection between the source (sxa, sxb) and drain (dx) pins of the device. when the enable pin is pulled high, all switches are turned off. when the enables is pulled low, the select pin controls the signal path selection. the select pin (sel) controls the state of all four channels of the tmux1574 and determines which source pin is connected to the drain pins. when the select pin is pulled low, the sxa pin conducts to the corresponding dx pins. when the select pin is pulled high, the sxb pin conducts to the corresponding dx pins. the tmux1574 has internal weak pull-down resistors (6 m ) to gnd so that it powers-on in a known state. 8.5 truth tables table 1 shows the truth table for the tmux1574. table 1. tmux1574 truth table inputs selected source pins connected to drain pins (dx) en sel 0 0 sxa connected to dx 0 1 sxb connected to dx 1 x hi-z (off) advance information
16 tmux1574 scds391 ? october 2018 www.ti.com product folder links: tmux1574 submit documentation feedback copyright ? 2018, texas instruments incorporated 9 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 9.1 application information the tmux15xx family offers high-speed system performance across a wide operating supply (1.5 v to 5.5 v) and operating temperature (-40 c to +125 c). the tmux1574 supports a number of features that improve system performance such as 1.8 v logic compatibility , supports input voltages beyond supply , fail-safe logic , and powered-off protection up to 3.6 v . these features make the tmux15xx a family of protection multiplexers and switches that can reduce system complexity, board size, and overall system cost. 9.2 typical application common applications that require the features of the tmux1574 include multiplexing various protocols from a possessor or mcu such as spi, jtag, or standard gpio signals. the device provides good isolation performance when the device is powered, and unpowered with source (sx) and drain (dx) pins below 3.6 v. the added benefit of powered-off protection allows a system to minimize complexity by eliminating the need for power sequencing in hot-swap and live insertion applications. the example shown in figure 12 illustrates the use of the tmux1574 to multiplex an spi bus to multiple flash memory devices. figure 12. multiplexing flash memory 9.2.1 design requirements for this design example, use the parameters listed in table 2. table 2. design parameters parameters values supply (v dd ) 3.3 v input / output signal range 0 v to 3.3 v control logic thresholds 1.8 v compatible advance information processor gnd v dd v dd 1.8 v 1.8v logic i/o sel gnd spi port d1 d2 d3 d4 ram cpu peripherals 0.1f en s1b s2b s3b s4b flash device #2 s1a s2a s3a s4a flash device #1 miso mosi sclk ss miso mosi sclk ss v i/o 3.3 v 3.3 v
17 tmux1574 www.ti.com scds391 ? october 2018 product folder links: tmux1574 submit documentation feedback copyright ? 2018, texas instruments incorporated 9.2.2 detailed design procedure the tmux1574 can be operated without any external components except for the supply decoupling capacitors. the tmux1574 has internal weak pull-down resistors (6 m ) to gnd so that it powers-on with the switches in a known state. all inputs signals passing through the switch must fall within the recommend operating conditions of the tmux1574 including signal range and continuous current. for this design example, with a supply of 3.3 v, the signals can range from 0 v to 5.5 v when the device is powered. this example can also utilize the powered- off protection feature and the inputs can range from 0 v to 3.6 v when v dd = 0 v. the max continuous current can be 25 ma. due to the voltage range and high speed capability, the tmux1574example is suitable for use in spi and jtag applications beyond the 100 mhz maximum in a typical application. 10 power supply recommendations the tmux1574 operates across a wide supply range of 1.5 v to 5.5 v. do not exceed the absolute maximum ratings because stresses beyond the listed ratings can cause permanent damage to the devices. power-supply bypassing improves noise margin and prevents switching noise propagation from the v dd supply to other components. good power-supply decoupling is important to achieve optimum performance. for improved supply noise immunity, use a supply decoupling capacitor ranging from 0.1 f to 10 f from v dd to ground. place the bypass capacitors as close to the power supply pins of the device as possible using low-impedance connections. ti recommends using multi-layer ceramic chip capacitors (mlccs) that offer low equivalent series resistance (esr) and inductance (esl) characteristics for power-supply decoupling purposes. for very sensitive systems, or for systems in harsh noise environments, avoiding the use of vias for connecting the capacitors to the device pins may offer superior noise immunity. the use of multiple vias in parallel lowers the overall inductance and is beneficial for connections to ground planes. advance information
18 tmux1574 scds391 ? october 2018 www.ti.com product folder links: tmux1574 submit documentation feedback copyright ? 2018, texas instruments incorporated 11 layout 11.1 layout guidelines when a pcb trace turns a corner at a 90 angle, a reflection can occur. a reflection occurs primarily because of the change of width of the trace. at the apex of the turn, the trace width increases to 1.414 times the width. this increase upsets the transmission-line characteristics, especially the distributed capacitance and self ? inductance of the trace which results in the reflection. not all pcb traces can be straight and therefore some traces must turn corners. figure 13 shows progressively better techniques of rounding corners. only the last example (best) maintains constant trace width and minimizes reflections. figure 13. trace example route the high-speed signals using a minimum of vias and corners which reduces signal reflections and impedance changes. when a via must be used, increase the clearance size around it to minimize its capacitance. each via introduces discontinuities in the signal ? s transmission line and increases the chance of picking up interference from the other layers of the board. be careful when designing test points, through- hole pins are not recommended at high frequencies. do not route high speed signal traces under or near crystals, oscillators, clock signal generators, switching regulators, mounting holes, magnetic devices or ics that use or duplicate clock signals. avoid stubs on the high-speed signals traces because they cause signal reflections. route all high-speed signal traces over continuous gnd planes, with no interruptions. avoid crossing over anti-etch, commonly found with plane splits. when working with high frequencies, a printed circuit board with at least four layers is recommended; two signal layers separated by a ground and power layer as shown in figure 14 . figure 14. example layout the majority of signal traces must run on a single layer, preferably signal 1. immediately next to this layer must be the gnd plane, which is solid with no cuts. avoid running signal traces across a split in the ground or power plane. when running across split planes is unavoidable, sufficient decoupling must be used. minimizing the number of signal vias reduces emi by reducing inductance at high frequencies. figure 15 illustrates an example of a pcb layout with the tmux1574. some key considerations are: worst better best 1w min. w 2w advance information signal 1 gnd plane power plane signal 2
19 tmux1574 www.ti.com scds391 ? october 2018 product folder links: tmux1574 submit documentation feedback copyright ? 2018, texas instruments incorporated layout guidelines (continued) decouple the v dd pin with a 0.1- f capacitor, placed as close to the pin as possible. make sure that the capacitor voltage rating is sufficient for the v dd supply. high-speed switches require proper layout and design procedures for optimum performance. keep the input lines as short as possible. use a solid ground plane to help reduce electromagnetic interference (emi) noise pickup. do not run sensitive analog traces in parallel with digital traces. avoid crossing digital and analog traces if possible, and only make perpendicular crossings when necessary. 11.2 layout example figure 15. example layout sels1a s1b d1 s2a s2b vdd en s4a s4b d4 s3a gnd tmux1574 c d3 via to gnd plane wide (low inductance) trace for power d2 s3b advance information
20 tmux1574 scds391 ? october 2018 www.ti.com product folder links: tmux1574 submit documentation feedback copyright ? 2018, texas instruments incorporated 12 device and documentation support 12.1 documentation support 12.1.1 related documentation texas instruments, improve stability issues with low con multiplexers . texas instruments, simplifying design with 1.8 v logic muxes and switches . texas instruments, eliminate power sequencing with powered-off protection signal switches . texas instruments, system-level protection for high-voltage analog multiplexers . texas instruments, high-speed interface layout guidelines . texas instruments, high-speed layout guidelines . texas instruments, qfn/son pcb attachment . texas instruments, quad flatpack no-lead logic packages . 12.2 receiving notification of documentation updates to receive notification of documentation updates, navigate to the device product folder on ti.com. in the upper right corner, click on alert me to register and receive a weekly digest of any product information that has changed. for change details, review the revision history included in any revised document. 12.3 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 12.4 trademarks e2e is a trademark of texas instruments. 12.5 electrostatic discharge caution this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.6 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. advance information
21 tmux1574 www.ti.com scds391 ? october 2018 product folder links: tmux1574 submit documentation feedback copyright ? 2018, texas instruments incorporated 13 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation. advance information
package option addendum www.ti.com 19-oct-2018 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples pTMUX1574PWR active tssop pw 16 2000 tbd call ti call ti -40 to 125 TMUX1574PWR preview tssop pw 16 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 mux1574 tmux1574rsvr preview uqfn rsv 16 3000 green (rohs & no sb/br) cu nipdauag level-1-260c-unlim -40 to 125 1574 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) rohs: ti defines "rohs" to mean semiconductor products that are compliant with the current eu rohs requirements for all 10 rohs substances, including the requirement that rohs substance do not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, "rohs" products are suitable for use in specified lead-free processes. ti may reference these types of products as "pb-free". rohs exempt: ti defines "rohs exempt" to mean products that contain lead but are compliant with eu rohs pursuant to a specific eu rohs exemption. green: ti defines "green" to mean the content of chlorine (cl) and bromine (br) based flame retardants meet js709b low halogen requirements of <=1000ppm threshold. antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release.
package option addendum www.ti.com 19-oct-2018 addendum-page 2 in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
www.ti.com package outline c 14x 0.65 2x 4.55 16x 0.30 0.19 typ 6.6 6.2 1.2 max 0.15 0.05 0.25 gage plane -8 0 b note 4 4.5 4.3 a note 3 5.1 4.9 0.75 0.50 (0.15) typ tssop - 1.2 mm max height pw0016a small outline package 4220204/a 02/2017 1 8 9 16 0.1 c a b pin 1 index area see detail a 0.1 c notes: 1. all linear dimensions are in millimeters. any dimensions in parenthesis are for reference only. dimensioning and tolerancing per asme y14.5m. 2. this drawing is subject to change without notice. 3. this dimension does not include mold flash, protrusions, or gate burrs. mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. this dimension does not include interlead flash. interlead flash shall not exceed 0.25 mm per side. 5. reference jedec registration mo-153. seating plane a 20 detail a typical scale 2.500
www.ti.com example board layout 0.05 max all around 0.05 min all around 16x (1.5) 16x (0.45) 14x (0.65) (5.8) (r0.05) typ tssop - 1.2 mm max height pw0016a small outline package 4220204/a 02/2017 notes: (continued) 6. publication ipc-7351 may have alternate designs. 7. solder mask tolerances between and around signal pads can vary based on board fabrication site. land pattern example exposed metal shown scale: 10x symm symm 1 8 9 16 15.000 metal solder mask opening metal under solder mask solder mask opening exposed metal exposed metal solder mask details non-solder mask defined (preferred) solder mask defined
www.ti.com example stencil design 16x (1.5) 16x (0.45) 14x (0.65) (5.8) (r0.05) typ tssop - 1.2 mm max height pw0016a small outline package 4220204/a 02/2017 notes: (continued) 8. laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. ipc-7525 may have alternate design recommendations. 9. board assembly site may have different recommendations for stencil design. solder paste example based on 0.125 mm thick stencil scale: 10x symm symm 1 8 9 16

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